Field effect transistors (FETs) typically include a source region, a drain region and a channel region interconnecting the source region and the drain region. A gate regulates current flow through the channel. In the case of a nanowire FET, the channel region is made up of one or more nanowire channels.
With a conventional gate-all-around nanowire FET, the gate line defines the channel region and the portion of the nanowire extending from the gate forms the device source or drain. Contacts to the source and drain are typically done by forming a silicide over the nanowire. To obtain high circuit densities both the gate length and the spacing between adjacent gates (also referred to as pitch) have to be minimized. As a result the contact length is limited to the spacing between gates. Current transfer from a semiconductor to the contact (as is the case from the nanowire source or drain to the silicide over the nanowire) can be characterized based on transfer length LT which is the distance over which most of the current transfers from the semiconductor into the contact (or vice-a-versa). See for example, D. K. Schroder, “Semiconductor Material and Device Characterization,” 2nd Ed., John Wiley & sons, 1998, pg. 150 (hereinafter “Schroder”). As illustrated in Schroder, decreasing the length of the contact will introduce an unacceptable amount of resistance. Accordingly, with a conventional source and drain contact scheme, the contact length needs to be at least as long as the transfer length LT. This requirement puts a limit on how small the length of the source or drain can be and therefore limits the device pitch.
Therefore, fabrication processes which permit source and drain contact scaling without violating this transfer length LT limitation would be desirable.